VERILOG CODE FOR CLOCK DIVIDER

In some of the applications we don't want a very high speed clock and the problem occurs when we have a fixed frequency clock then we have to use a module that divide the frequency of the clock by a certain factor that satisfies the requirement .It seems to b a difficult task but believe me it is a very simple thing to do and it can solve your problems.Clock Divider can be used in many applications like if you are implementing a Traffic signal on spartan board then you want to divide your clock frequency as you don't like the signals to change their states in less than a thousand part of a second the simple solution is he CLOCK DIVIDER.so,here is the verilog cod for the code.

All you have to do is to put the value of the factor by which you want to divide the clock into the parameter named "DIVIDER"


module dclock(clk, reset, clko);
    input clk;
    input reset;
    output clko;
parameter divider=6;
reg clko;
integer i=0;

always@(posedge clk)
begin

if(reset==1)
begin
clko=0;
i=0;
end


else if(i<((divider/2)-1))
begin
clko=0;
i=i+1;
end

else if(i==((divider/2)-1))

begin
clko=1;
i=i+1;
end

else if(i<(divider-1))
begin
clko=1;
i=i+1;
end
else if(i==divider-1)
begin
clko=0;
i=0;
end


end

endmodule